M32C8A Datasheet, PDF (231/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
17.1.1.3 Serial Data Logic Inverse
When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted
for transmit operation. A read from the UiRB register returns the inverted logic of receive data. Figure 17.16
shows an example of serial data logic inverse operation.
(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)
"H"
Serial clock
"L"
TXDi ^"H"
(not inverted) _"L"
RXDi ^"H"
(not inverted) _"L"
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiLCH bit is set to 1 (inverted)
"H"
Serial clock
"L"
TXDi ^"H"
(inverted) _"L"
D0
D1
D2
D3
D4
D5
D6
D7
RXDi ^"H"
(inverted) _"L"
D0
D1
D2
D3
D4
D5
D6
D7
The above applies under the following conditions:
- CKPOL bit in the UiC0 register is set to 0 (transmit data is output at the falling edge and received data is input at the rising edge)
- UFORM bit in the UiC0 register is set to 0 (LSB first).
Figure 17.16 Serial Data Logic Inverse
Rev.1.00 Jul 15, 2007 Page 214 of 352
REJ09B0385-0100