M32C8A Datasheet, PDF (104/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
9. Clock Generation Circuits
Table 9.5 Operation Mode Setting
CPU Clock
Source
Operating Mode
Oscillation Control
Selector
CM0 Register
PLC0
CM2
CM1
CM0
Register Register Register ^Register
CM05 CM04 PLC07 CM21⁽¹⁾ CM17 CM07
Main clock Main clock mode
0
−
−
0
0
0
PLL clock
PLL mode
0
−
1
0
1
0
Low-speed mode
0
1
−
−
−
1
Sub clock
Low power
1
1
0
−
0
1
consumption mode
On-chip oscillator mode 0
−
−
1
−
0
On-chip
On-chip oscillator low-
1
−
0
1
0
0
oscillator clock _{power consumption}
mode
−: Can be set to either 0 or 1
NOTE:
1. The CM21 bit in the CM2 register has both the oscillation control and selector functions.
9.5.2 Wait Mode
In wait mode, the CPU and watchdog timer stop operating. If the PM22 bit in the PM2 register is set to 1 (on-
chip oscillator clock as watchdog timer count source), the watchdog timer continues operating. Since the main
clock, sub clock, and on-chip oscillator clock continue running, peripheral functions using these clocks as their
clock source also continue to operate.
9.5.2.1 Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait mode), fAD, f1, f8, and f32 stop in
wait mode. f2n, which uses the clock selected by the CM21 bit in the CM2 register as its clock source, also
stops in wait mode. Power consumption can be reduced by stopping these peripheral clocks. f2n, which uses
the XIN clock (fXIND) or on-chip oscillator clock as its clock source, and fC32 do not stop even in wait mode.
9.5.2.2 Entering Wait Mode
To enter wait mode with the CM02 bit in the CM0 register set to 1, set bits MCD4 to MCD0 in the MCD
register for the CPU clock frequency to be 10 MHz or less after dividing the main clock.
Figure 9.14 shows a procedure to enter wait mode.
Rev.1.00 Jul 15, 2007 Page 87 of 352
REJ09B0385-0100