M32C8A Datasheet, PDF (257/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
17.1.4.3 Clock Phase Setting Function
The clock polarity and clock phase are selected from four combinations of the CKPH and CKPOL bits in the
UiSMR3 register (i = 0 to 4). The master must have the same serial clock polarity and phase as the slaves
involved in the communication. Figure 17.29 shows a transmit and receive operation timing.
(1) When the CKPH = 0 (no clock delay)
“H”
CLKi I/O (CKPOL = 0)
“L”
“H”
CLKi I/O (CKPOL = 1)
“L”
In master mode
(internal clock)
(DINC = 0)
“H”
SSi input pin
“L”
“H”
TXDi output
“L”
D0
D1
D2
D3
D4
D5
D6
D7
Receive data
input timing
“H”
SSi input pin
“L”
In slave mode
“H”
(external clock) STXDi output ⁽¹⁾
undefined D0
D1
D2
D3
D4
D5
D6
D7
(DINC = 1)
“L” _Hi-Z
Hi-Z
Receive data
input timing
(2) When the CKPH = 1 (clock delay)
“H”
CLKi I/O (CKPOL = 0)
“L”
“H”
CLKi I/O (CKPOL = 1)
“L”
In master mode
(internal clock)
(DINC = 0)
“H”
SSi input pin
“L”
“H”
TXDi output
“L”
D0
D1
D2
D3
D4
D5
D6
Receive data
input timing
“H”
SSi input pin
“L”
In slave mode
(external clock)
(DINC = 1)
STXDi
output ⁽¹⁾
“H”
“L” _Hi-Z
D0
D1
D2
D3
D4
D5
D6
i=0 to 4
Receive data
input timing
CKPH, DINC: bits in the UiSMR3 register
CKPOL: bit in the UiC0 register
NOTE:
1. P7_0 and P7_1 are N-channel open drain output ports. They must be pulled up externally to output data.
D7
D7
Hi-Z
Figure 17.29 Transmit and Receive Operation Timing in Special Mode 2
Rev.1.00 Jul 15, 2007 Page 240 of 352
REJ09B0385-0100