M32C8A Datasheet, PDF (32/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
1. Overview
1.5 Pin Functions
Table 1.11 Pin Functions (1) (100-Pin Package and 144-Pin Package)
Item
Pin Name
Power supply
Analog power
supply input
Reset input
VCC1,VCC2
VSS
AVCC
AVSS
RESET
CNVSS
CNVSS
External data
bus width
select input
Bus control
Pins
BYTE
D0 to D7
D8 to D15
A0 to A22
A23
A0/D0 to
A7/D7
A8/D8 to
A15/D15
CS0 to CS3
WRL/WR
WRH/BHE
RD
ALE
HOLD
HLDA
RDY
I/O
Type
−
−
I
I
I
I/O
I/O
O
O
I/O
I/O
O
Supply
Voltage
−
VCC1
VCC1
VCC1
VCC1
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
Description
Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin.
The input condition of VCC1 ≥ VCC2 must be met.
Power supply input pins to the A/D converter and D/A converter.
Connect the AVCC pin to VCC1, and the AVSS pin to VSS.
The MCU is placed in a reset state when applying an “L” signal to
the RESET pin.
This pin switches processor mode. Apply an “H” signal to the
CNVSS pin to start up in microprocessor mode.
This pin switches data bus width in external memory space 3. A
data bus is 16 bits wide when the BYTE pin is held “L” and 8 bits
wide when it is held “H”.
Data (D0 to D7) input/output pins while accessing an external
memory space with separate bus.
Data (D8 to D15) inputs/output pins while accessing an external
memory space with 16-bit separate bus.
Address bits (A0 to A22) output pins.
Inverted address bit (A23) output pin.
Data (D0 to D7) input/output and 8 low-order address bits (A0 to
A7) output are performed by time-sharing these pins while
accessing an external memory space with multiplexed bus.
Data (D8 to D15) input/output and 8 middle-order address bits (A8
to A15) output are performed by time-sharing these pins while
accessing an external memory space with 16-bit multiplexed bus.
Chip-select signal output pins used to specify external devices.
O VCC2 _{WRL, WRH, (WR, BHE) and RD signal output pins. WRL and WRH}
can be switched with WR and BHE by program.
• WRL, WRH and RD are selected:
If external data bus is 16 bits wide, data is written to an even
address in external memory space while an “L” is output from the
WRL pin. Data is written to an odd address while an “L” is output
from the WRH pin.
Data is read while an “L” is output from the RD pin.
• WR, BHE and RD are selected:
Data is written while an “L” is output from the WR pin.
Data is read while an “L” is output from the RD pin.
Data in odd address is accessed while an “L” is output from the
BHE pin. Select WR, BHE and RD when an external data bus is
8 bits wide.
O VCC2 ALE signal is used for the external devices to latch address signals
when the multiplexed bus is selected.
I VCC2 _{The MCU is placed in a hold state while an “L” signal is applied to}
the HOLD pin.
O VCC2 The HLDA pin outputs an “L” while the MCU is placed in a hold
state
I VCC2 _{Bus is placed in a wait state while an “L” signal is applied to the}
RDY pin.
Rev.1.00 Jul 15, 2007 Page 15 of 352
REJ09B0385-0100