M32C8A Datasheet, PDF (260/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
Start initial setting
I flag = 0
UiMR register: bits SMD2 to SMD0 = 001b
CKDIR bit = 1
IOPOL bit = 0
UiSMR register: bits 6 to 0 = 0000000b
SCLKDIV bit
UiSMR2 register: bits 6 to 0 = 0000000b
SU1HIM bit
UiSMR3 register = 00h
UiSMR4 register = 00h
UiC0 register: bits CLK1 and CLK0 = 00b
CRD bit = 1
NCH bit
CKPOL bit = 0
UFORM bit = 0
UiBRG register = 00h
UiC1 register: TE bit = 0
RE bit = 0
UiIRS bit
UiRRM bit = 0
UiLCH bit = 0
SCLKSTPB bit = 0
SiTIC register: bits ILVL2 to ILVL0
IR bit = 0
SiRIC register: bits ILVL2 to ILVL0
IR bit = 0
Pin setting in the Function Select Registers
I flag = 1
UiC1 register: TE bit = 1
RE bit = 1
End initial setting
Interrupt disabled
Clock synchronous mode
Select external clock
Clock division synchronous bit⁽¹⁾
External clock synchronous enable bit⁽¹⁾
CTS function disabled
Data output select bit
Transmit operation disabled
Receive operation disabled
UARTi transmit interrupt source select bit
Clock-divided synchronization stopped
Transmit interrupt priority level select bits
Interrupt not requested
Receive interrupt priority level select bits
Interrupt not requested
Interrupt enabled
Transmit operation enabled
Receive operation enabled
Transmit/receive operation starts when a trigger is input to the
CTSi pin after writing data to the UiTB register.
Read the UiRB register when a receive operation is completed.
i = 0 to 4
NOTE:
1. The external clock synchronization function is determined by the combination of the SCLKDIV bit in the UiSMR register
and the SU1HIM bit in the UiSMR2 register. Refer to the table " Clock-Divided Synchronous Function Select" for details.
Figure 17.30 Register Settings in GCI Mode
Rev.1.00 Jul 15, 2007 Page 243 of 352
REJ09B0385-0100