M32C8A Datasheet, PDF (82/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
8. Bus
8.2.8 External Bus States when Accessing Internal Space
Table 8.9 lists external bus states when the internal space is accessed.
Table 8.9 External Bus States when Accessing Internal Space
Item
State when Accessing SFR and Internal RAM
A0 to A22, A23
D0 to D15
RD, WR, WRL, WRH
BHE
CS
ALE
Hold the last accessed address in the external space
High-impedance
Outputs “H”
Holds the output level at the time when the MCU accessed the external
space or SFR area for the last time
Outputs “H”
Outputs ALE signal
8.2.9 BCLK Output
The bus clock can be output from the BCLK pin in microprocessor mode. To output the bus clock, set the
PM07 bit in the PM0 register to 0 (BCLK output) and bits CM01 and CM00 in the CM0 register to 00b (I/O
port P5_3).
Refer to 9. Clock Generation Circuits for details.
Rev.1.00 Jul 15, 2007 Page 65 of 352
REJ09B0385-0100