M32C8A Datasheet, PDF (236/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
(1) Example of the transmit operation timing in 8-bit data length (parity enabled, 1 stop bit)
TC
Internal transmit
clock
TE bit in the
1
UiC1 register
0
TI bit in the UiC1
1
register
0
“H”
CTSi input
“L”
“H”
TXDi output
“L”
TXEPT bit in the
1
UiC0 register
0
IR bit in the
1
SiTIC register
0
Write data to UiTB register
Transfer data from UiTB register to UARTi transmit shift register
Start bit
Stop bit ^{Transmission stops because TE = 0}
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit
ST D0
Set to 0 by an interrupt request acknowledgement or by program
The above applies under the following conditions:
- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)
- UiC0 register: CRD bit = 0 and CRS bit = 0 (CTS function used)
- UiC1 register: UiIRS bit = 1 (transmit interrupt is generated when the transmit operation is completed)
(2) Example of the transmit operation timing in 9-bit data length (parity disabled, 2 stop bit)
TC
Internal transmit
clock
TE bit in the
1
UiC1 register
0
TI bit in the UiC1
1
register
0
“H”
TXDi output
“L”
TXEPT bit in the
1
UiC0 register
0
IR bit in the
1
SiTIC register
0
Write data to UiTB register
Transfer data from UiTB register to UARTi transmit shift register
Start bit
Stop bits
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0
Set to 0 by an interrupt request acknowledgement or by program
The above applies under the following conditions:
- UiMR register: PRYE bit = 0 (parity disabled), STPS bit = 1 (2 stop bits)
- UiC0 register: CRD bit = 1 (CTS function disabled)
- UiC1 register: UiIRS bit = 0 (transmit interrupt is generated when no data in the UiTB register)
TC = ^{16(m + 1)}
fj
i = 0 to 4
fj: f1, f8, f2n⁽¹⁾, fEXT
fEXT: clock input to the CLKi pin when the external clock is selected
m: setting value of the UiBRG register (00h to FFh)
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.18 Transmit Operation in UART Mode
Rev.1.00 Jul 15, 2007 Page 219 of 352
REJ09B0385-0100