SH7618 Datasheet, PDF (97/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 5 Exception Handling
Section 5 Exception Handling
5.1 Overview
5.1.1 Types of Exception Handling and Priority
Exception handling is started by four sources: resets, address errors, interrupts and instructions and
have the priority, as shown in table 5.1. When several exceptions are detected at once, they are
processed according to the priority.
Table 5.1 Types of Exceptions and Priority
Exception
Exception Source
Priority
Reset
Power-on reset
High
H-UDI reset
Interrupt
User break (break before instruction execution)
Address error CPU address error (instruction fetch)
Instruction
General illegal instructions (undefined code)
Illegal slot instruction (undefined code placed immediately after a
delayed branch instruction*¹ or instruction that changes the PC value*²)
Trap instruction (TRAPA instruction)
Address error CPU address error (data access)
Interrupt
User break (break after instruction execution or operand break)
NMI
H-UDI
IRQ
On-chip
peripheral
modules:
Watchdog timer (WDT)
Ether controller (EtherC and E-DMAC)
Compare match timer 0 and 1 (CMT0 and CMT1)
Serial communication interface with FIFO (SCIF0,
SCIF1, and SCIF2)
Host interface (HIF)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
BRAF.
2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,
TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.
Rev. 6.00 Jun. 12, 2007 Page 65 of 610
REJ09B0131-0600