SH7618 Datasheet, PDF (390/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value
R/W Description
5
CTSIO 0
R/W CTS Port Input/Output Control
Controls the CTS pin in combination with the CTSDT bit
in this register and the MCE bit in SCFCR.
This bit is reserved in SCPTR_2 of SCIF channel 2
since SCIF channel 2 does not support the flow control.
4
CTSDT *
R/W CTS Port Data
Controls the CTS pin in combination with the CTSIO bit
in this register and the MCE bit in SCFCR. Select the
CTS pin function in the PFC (pin function controller)
beforehand.
MCE CTSIO CTSDT: CTS pin state
0
0
×:
Input (initial state)
0
1
0:
Low level output
0
1
1:
High level output
1
×
×:
Input to modem control logic
×: Don't care
The CTS pin state is read from this bit instead of the set
value. This bit is reserved in SCPTR_2 of SCIF channel
2 since SCIF channel 2 does not support the flow
control.
3
SCKIO 0
R/W SCK Port Input/Output Control
Controls the SCK pin in combination with the SCKDT
bit in this register, the C/A bit in SCSMR, and bits CKE1
and CKE0 in SCSCR.
Rev. 6.00 Jun. 12, 2007 Page 358 of 610
REJ09B0131-0600