SH7618 Datasheet, PDF (241/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 9 Watchdog Timer (WDT)
9.2 Register Descriptions
The WDT has the following two registers. For details on the addresses of these registers and the
states of these registers in each processing state, see section 20, List of Registers.
• Watchdog timer counter (WTCNT)
• Watchdog timer control/status register (WTCSR)
9.2.1 Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an
overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time
mode. WTCNT is not initialized by an internal power-on reset due to the WDT overflow. WTCNT
is initialized to H'00 by a power-on reset input to the pin and an H-UDI reset.
Use a word access to write to WTCNT, with H'5A in the upper byte. Use a byte access to read
WTCNT.
Note: The writing method for WTCNT differs from other registers so that the WTCNT value
cannot be changed accidentally. For details, see section 9.2.3, Notes on Register Access.
9.2.2 Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
counting, bits to select the timer mode and overflow flags, and enable bits.
WTCSR holds its value in the internal reset state due to the WDT overflow. WTCSR is initialized
to H'00 by a power-on reset input to the pin and an H-UDI reset. To use it for counting the clock
settling time when leaving software standby mode, WTCSR holds its value after a counter
overflow.
Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read
WTCSR.
Note: The writing method for WTCNT differs from other registers so that the WTCNT value
cannot be changed accidentally. For details, see section 9.2.3, Notes on Register Access.
Rev. 6.00 Jun. 12, 2007 Page 209 of 610
REJ09B0131-0600