SH7618 Datasheet, PDF (314/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name value R/W Description
18
RFF2
1
R/W Receive Frame Number Flow Control Threshold
17
RFF1
1
16
RFF0
1
R/W 000: When one receive frame has been stored in the
R/W
receive FIFO
001: When two receive frames have been stored in
the receive FIFO
:
:
110: When seven receive frames have been stored in
the receive FIFO
111: When eight receive frames have been stored in
the receive FIFO
15 to 3 
All 0

Reserved
These bits are always read as 0. The write value
should always be 0.
2
RFD2
0
R
Receive Byte Flow Control Threshold
1
RFD1
0
R
000: When (256 − 64) bytes of data is stored in the
0
RFD0
0
R
receive FIFO
001: When (512 − 64) bytes of data is stored in the
receive FIFO (Setting prohibited in SH7618,
setting enabled in SH7618A)
Other than above: Setting prohibited
12.2.19 Transmit Interrupt Register (TRIMD)
TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back
completion for each frame using the TWB bit in EESR and an interrupt on transmit operations.
Initial
Bit
Bit Name value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
TIS
0
R/W Transmit Interrupt Setting
0: Write-back completion for each frame is not
notified
1: Write-backed completion for each frame using the
TWB bit in EESR is notified
Rev. 6.00 Jun. 12, 2007 Page 282 of 610
REJ09B0131-0600