SH7618 Datasheet, PDF (338/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.4.2 Usage Notes on SH-Ether Transmit-FIFO Underflow
In the transmission operation of the on-chip E-DMAC of the SH-Ether, if the E-DMAC cannot
acquire bus-mastership due to occupancy of the bus by a bus master other than the E-DMAC, data
are not writable to the transmit FIFO and an underflow occurs. The expected operation from that
point is as follows: on obtaining the bus mastership, the E-DMAC resumes transmission of the
remaining data for transmission; on completion of the DMA transfer, it writes back to the
corresponding descriptor, and then fetches the next transmit descriptor. However, if the size of the
transmit FIFO set by the FIFO depth register (FDR) ≤ maximum frame length for transmission
(1518 bytes), the E-DMAC may stop operating even if the transmit request bit (TR) in the E-
DMAC transmit request register (EDTRR) is set to 1, according to the relationship between the
length of the remaining frame data and the value of the transmit FIFO pointer.
The relationship between the stoppage of E-DMAC operation and the state of the transmit FIFO is
shown below.
The data for transmission, which are placed in external memory (transmit buffer), are DMA-
transferred by the E-DMAC to the transmit FIFO and output from the MII pin via the EtherC
module. The transmit FIFO write pointer (WP) is used when the E-DMAC writes the data for
transmission to the transmit FIFO, and the transmit FIFO read pointer (RP) is used when the
EtherC module reads the data for transmission from the transmit FIFO.
1. After a software reset, the transmit FIFO will have been initialized, and WP and RP will hold
the minimum and maximum values, respectively, of the transmit FIFO capacity.
2. When the E-DMAC starts DMA transfer, WP is incremented when the data for transmission
are written to the transmit FIFO. On the other hand, RP is incremented when the data written
to the transmit FIFO are read out by the EtherC module.
Note: The transmit FIFO only stores the data of a single frame that is being processed. It does
not store data extending over multiple frames. This means that the E-DMAC does not
transfer the next frame to the transmit FIFO until the data of the frame being processed are
read from the transmit FIFO.
3. If the E-DMAC fails to get the bus mastership for a system-related reason, the DMA transfer
does not proceed and a transmit underflow occurs (WP = RP < frame length). Read access to
the transmit FIFO by the EtherC is then terminated and RP is initialized (to the maximum
value of the size of the transmit FIFO).
4. On again acquiring the bus mastership, the E-DMAC resumes DMA transfer of the remaining
data of the frame. However, if the transmit FIFO becomes full despite a failure to write all of
the remaining frame data from the point when the transmit FIFO underflowed, the E-DMAC
waits for the transmit FIFO to become empty before transferring further remaining data.
Rev. 6.00 Jun. 12, 2007 Page 306 of 610
REJ09B0131-0600