SH7618 Datasheet, PDF (438/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 15 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
0
AC
0/1
R/W HIFRAM Access Exclusive Control
Controls accessing of HIFRAM by the on-chip CPU for
the HIFRAM bank selected by the BMD and BSEL bits
in HIFSCR as the bank allowed to be accessed by this
LSI.
0: The on-chip CPU can perform reading/writing of
HIFRAM.
1: When an HIFRAM read/write operation by the on-
chip CPU occurs, the CPU enters the wait state, and
execution of the instruction is halted until this bit is
cleared to 0.
When booted in non-HIF boot mode, the initial value of
this bit is 0.
When booted in HIF boot mode, the initial value of this
bit is 1. After an external device writes a boot program
to HIFRAM via the HIF, clearing this bit to 0 boots the
on-chip CPU from HIFRAM.
When 1 is written to this bit by an external device, H'A5
should be written to bits 7 to 0 to prevent erroneous
writing.
15.4.10 HIFDREQ Trigger Register (HIFDTR)
HIFDTR is a 32-bit register. Writing to HIFDTR by the on-chip CPU asserts the HIFDREQ pin.
HIFDTR cannot be accessed by an external device.
Initial
Bit
Bit Name Value R/W
31 to 1 —
All 0
R*¹
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 6.00 Jun. 12, 2007 Page 406 of 610
REJ09B0131-0600