SH7618 Datasheet, PDF (340/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
(1) Countermeasure
This problem occurs under this condition:
size of transmit FIFO set in the FIFO depth register (FDR) ≤ maximum length of frame for
transmission (1518bytes).
To release the E-DMAC from the stopped state due to this problem, execute a software reset to
initialize both the E-DMAC and EtherC modules.
Specific countermeasures are given below. An example for the case where the software does not
use TC interrupts in transmission processing is given as (2), and an example for the case with TC
interrupt-driven software is given as (3). Both methods require the addition of timeout processing
with a maximum specified time as the timeout limit, and are based on the countermeasures
explained in section 12.4.1, Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR).
The constant specified time corresponds to the timeout limit stated in section 12.4.1, Usage Notes
on SH-Ether EtherC/E-DMAC Status Register (EESR). The maximum specified time should be
set with reference to the maximum times taking retry processing into consideration, as given in
table 12.2. Derive n, the number of repetitions of the constant specified time, from this maximum
specified time. If transfer takes more than the maximum specified time, this indicates that the E-
DMAC has stopped due to a transmission underflow. In this case, execute a software reset to
initialize the EtherC and E-DMAC modules. Since the receiving side will also be initialized by the
software reset, the receiving side may require processing in a higher-level layer (e.g. TCP/IP).
Note: The countermeasure should be the one that best suits the structure of your driver and other
software.
(2) Countermeasure for the case where the software handles transmission without the aid
of TC interrupts
The countermeasure described under (a), Processing transmission without handling of the frame
transmission complete (TC) interrupt, below, is based on the method explained in the description
of bit 21 in (1) of section 12.4.1, Usage Notes on SH-Ether EtherC/E-DMAC Status Register
(EESR).
Rev. 6.00 Jun. 12, 2007 Page 308 of 610
REJ09B0131-0600