SH7618 Datasheet, PDF (265/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Initial
Bit
Bit Name Value R/W
16
TXF
0
R/W
15 to 13 
All 0
R
12
PRCEF 0
R/W
11, 10 
All 0
R
9
MPDE 0
R/W
8, 7

All 0
R
6
RE
0
R/W
Section 11 Ethernet Controller (EtherC)
Description
Transmit Flow Control Operating mode
0: Transmit flow control function is disabled
1: Transmit flow control function is enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
Permit Receive CRC Error Frame
0: A frame with a CRC error is received as a frame
with an error.
1: A frame with a CRC error is received as a frame
without an error.
For a frame with an error, a CRC error is reflected in
ECSR of the E-DMAC and the status of the receive
descriptor. For a frame without an error, the frame is
received as normal frame.
Reserved
These bits are always read as 0. The write value
should always be 0.
Magic Packet Detection Enable
Enables or disables Magic Packet detection by
hardware to allow activation from the Ethernet.
0: Magic Packet detection is not enabled
1: Magic Packet detection is enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
Reception Enable
If a frame is being received when this bit is switched
from receive function enabled (RE = 1) to disabled
(RE = 0), the receive function will be enabled until
reception of the corresponding frame is completed.
0: Receive function is disabled
1: Receive function is enabled
Rev. 6.00 Jun. 12, 2007 Page 233 of 610
REJ09B0131-0600