SH7618 Datasheet, PDF (351/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 13 Compare Match Timer (CMT)
13.3 Operation
13.3.1 Interval Count Operation
When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set
to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 13.2 shows the operation of the compare match counter.
CMCNT1 value
CMCOR1
Counter cleared by compare
match with CMCOR1
H'0000
Time
Figure 13.2 Counter Operation
13.3.2 CMCNT Count Timing
One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the Pφ clock
can be selected with bits CKS1 and CKS0 in CMCSR. Figure 13.3 shows the timing.
Peripheral operating
clock (Pφ)
Count clock
CMCNT1
Nth
clock
(N + 1)th
clock
N
Figure 13.3 Count Timing
N+1
Rev. 6.00 Jun. 12, 2007 Page 319 of 610
REJ09B0131-0600