SH7618 Datasheet, PDF (38/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 1 Overview
1.2 Block Diagram
Figure 1.1 is a block diagram of this LSI.
SuperH
CPU core
User break
controller
(UBC)
CPU bus (I clock)
Cache
access
controller
(CCN)
Cache
memory
4 kbytes
(SH7618)
16 kbytes
(SH7618A)
U memory
4 kbytes
Internal bus (B clock)
Bus state
controller
(BSC)
External bus
Peripheral
bus
controller
Ethernet
controller
direct memory
access
controller
(E-DMAC)
Transmit FIFO
(256 bytes (SH7618))
Receive FIFO
(512 bytes (SH7618A))
Ethernet controller
(EtherC)
Peripheral bus (P clock)
I/O port,
Pin function
controller
(PFC)
1-kbyte
SRAM
Host
interface
(HIF)
Serial
communication
interface
with FIFO
(SCIF)*1
Compare
match timer
(CMT)*2
User
debugging
interface
(H-UDI)
Interrupt
controller
(INTC)
Power-
down
mode
control
Watchdog Clock pulse
timer
generator
(WDT)
(CPG)
Notes: 1. SCIF includes three channels.
2. CMT includes two channels.
Figure 1.1 Block Diagram
Rev. 6.00 Jun. 12, 2007 Page 6 of 610
REJ09B0131-0600