SH7618 Datasheet, PDF (217/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 7 Bus State Controller (BSC)
Basic Timing for Memory Card Interface: Figure 7.31 shows the basic timing of the PCMCIA
IC memory card interface. If areas 5 and 6 in the physical space are specified as the PCMCIA
interface, accessing the common memory areas in areas 5 and 6 automatically accesses with the IC
memory card interface. If the external bus frequency (CKIO) increases, the setup times and hold
times for the address pins (A25 to A0), card enable signals (CE1A, CE2A, CE1B, CE2B), and
write data (D15 to D0) to the RD and WE signals become insufficient. To prevent this error, this
LSI can specify the setup times and hold times for areas 5 and 6 in the physical space
independently, using CS5BWCR and CS6BWCR. In the PCMCIA interface, as in the normal
space interface, a software wait or hardware wait can be inserted using the WAIT pin. Figure 7.32
shows the PCMCIA memory bus wait timing.
CKIO
A25 to A0
CExx
RD/WR
Read
RD
D15 to D0
Write
WE
D15 to D0
BS
Tpcm1
Tpcm1w
Tpcm1w
Tpcm1w
Tpcm2
Figure 7.31 Basic Access Timing for PCMCIA Memory Card Interface
Rev. 6.00 Jun. 12, 2007 Page 185 of 610
REJ09B0131-0600