SH7618 Datasheet, PDF (166/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10
PCW3
1
R/W Number of Access Wait Cycles
9
PCW2
0
R/W Specify the number of wait cycles to be inserted.
8
PCW1
1
R/W 0000: 3 cycles
7
PCW0
0
R/W ^{0001: 6 cycles}
0010: 9 cycles
0011: 12 cycles
0100: 15 cycles
0101: 18 cycles
0110: 22 cycles
0111: 26 cycles
1000: 30 cycles
1001: 33 cycles
1010: 36 cycles
1011: 38 cycles
1100: 52 cycles
1101: 60 cycles
1110: 64 cycles
1111: 80 cycles
6
WM
0
R/W External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
5, 4

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 6.00 Jun. 12, 2007 Page 134 of 610
REJ09B0131-0600