SH7618 Datasheet, PDF (43/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 1 Overview
Classifi-
cation Abbr.
Ethernet MDC
controller
MDIO
WOL
LNKSTA
EXOUT
Serial
TXD2 to
communic TXD0
ations
interface
with FIFO
RXD2 to
RXD0
SCK2 to
SCK0
RTS1 and
RTS0
CTS1 and
CTS0
Host
HIFD15 to
interface HIFD0
HIFCS
HIFRS
HIFWR
HIFRD
HIFINT
HIFMD
HIFDREQ
HIFRDY
HIFEBL
I/O Pin Name Description
Output Management Timing reference input for transfer information on the MDIO
Clock
pin
Input/ Management Bidirectional pin for management information transfer
output Data I/O
Output MAGIC Packet Indicates that a Magic Packet^TM* has received.
Receive
Input Link Status Input pin for a link state from a PHY LSI.
Output General output Output pin to external devices
Output Transmit Data Transmit data pins
Input Receive Data Receive data pins
Input/ Serial clock
output
Clock input pins
Output Transmit
Request
Modem control pin. Supported only by SCIF0 and SCIF1.
Input Transmit
Enable
Modem control pin. Supported only by SCIF0 and SCIF1.
Input/ HIF Data Bus Address, data, and command input/output pins for the HIF.
output
Input HIF Chip
Select
Chip select input for the HIF
Input HIF Register Controls the access type switching for the HIF.
Select
Input HIF Write
Write strobe signal
Input HIF Read
Read strobe signal
Output HIF Interrupt Interrupt request to external devices by the HIF
Input HIF Mode
Specifies HIF boot mode.
Output HIF DMAC
Transfer
Request
Requests DMAC transfer for the HIFRAM to external
devices.
Output HIF Boot
Ready
Indicates that a reset of the HIF has been cleared in this LSI
and the HIF is ready for accesses to it.
Input HIF Pin
Enable
HIF pins other than this pin are enabled by driving this pin
high.
Rev. 6.00 Jun. 12, 2007 Page 11 of 610
REJ09B0131-0600