SH7618 Datasheet, PDF (364/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
6
CHR
0
R/W Character Length
Selects 7-bit or 8-bit data in asynchronous mode. In the
synchronous mode, the data length is always eight bits,
regardless of the CHR setting.
0: 8-bit data
1: 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of the
transmit FIFO data register is not transmitted.
5
PE
0
R/W Parity Enable
Selects whether to add a parity bit to transmit data and to
check the parity of receive data, in asynchronous mode. In
synchronous mode, a parity bit is neither added nor
checked, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked*
Note: * When PE is set to 1, an even or odd parity bit is
added to transmit data, depending on the parity
mode (O/E) setting. Receive data parity is checked
according to the even/odd (O/E) mode setting.
4
O/E
0
R/W Parity mode
Selects even or odd parity when parity bits are added and
checked. The O/E setting is used only in asynchronous
mode and only when the parity enable bit (PE) is set to 1 to
enable parity addition and checking. The O/E setting is
ignored in synchronous mode, or in asynchronous mode
when parity addition and checking is disabled.
0: Even parity*¹
1: Odd parity*²
Notes:1. If even parity is selected, the parity bit is added
to transmit data to make an even number of 1s in
the transmitted character and parity bit
combined. Receive data is checked to see if it
has an even number of 1s in the received
character and parity bit combined.
2. If odd parity is selected, the parity bit is added to
transmit data to make an odd number of 1s in the
transmitted character and parity bit combined.
Receive data is checked to see if it has an odd
number of 1s in the received character and parity
bit combined.
Rev. 6.00 Jun. 12, 2007 Page 332 of 610
REJ09B0131-0600