SH7618 Datasheet, PDF (101/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

5.2 Resets
Section 5 Exception Handling
5.2.1 Types of Resets
Resets have priority over any exception source. As table 5.5 shows, a power-on reset initializes all
modules in this LSI.
Table 5.5 Reset Status
Conditions for Transition to
Reset State
Type
Power-on reset
H-UDI reset
WDT
RES Overflow
Low 
High Overflow
High Not
overflowed
H-UDI
Command CPU, INTC

Initialized

Initialized
Reset assert Initialized
command
Internal State
On-Chip
Peripheral
Module
PFC, I/O Port
Initialized Initialized
Initialized Initialized
Initialized Initialized
5.2.2 Power-On Reset
Power-On Reset by RES Pin: When the RES pin is driven low, this LSI enters the power-on
reset state. To reliably reset this LSI, the RES pin should be kept low for at least the oscillation
settling time when applying the power or when in standby mode (when the clock is halted) or at
least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and
all registers of on-chip peripheral modules are initialized.
In the power-on reset state, power-on reset exception handling starts when driving the RES pin
high after driving the pin low for the given time. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
of the status register (SR) are set to H'F (B'1111).
4. The values fetched from the exception handling vector table are set in PC and SP, then the
program starts.
Be certain to always perform power-on reset exception handling when turning the system power
on.
Rev. 6.00 Jun. 12, 2007 Page 69 of 610
REJ09B0131-0600