SH7618 Datasheet, PDF (389/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
14.3.11 Serial Port Register (SCSPTR)
SCSPTR is a 16-bit register that controls input/output and data for the pins multiplexed to the
SCIF function. Bits 7 and 6 can control the RTS pin, bits 5 and 4 can control the CTS pin, and bits
3 and 2 can control the SCK pin. Bits 1 and 0 can be used to read the input data from the RxD pin
and to output data to the TxD pin, so they control break of serial transfer. In addition to
descriptions of individual bits shown below, see section 14.6, Serial Port Register (SCSPTR) and
SCIF Pins.
SCSPTR can always be read from or written to by the CPU. Bits 7, 5, 3, and 1 in SCSPTR are
initialized by a power-on reset.
Bit
15 to 8
Bit Name

Initial
value
All 0
7
RTSIO 0
6
RTSDT *
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W RTS Port Input/Output Control
Controls the RTS pin in combination with the RTSDT bit
in this register and the MCE bit in SCFCR.
This bit is reserved in SCPTR_2 of SCIF channel 2
since SCIF channel 2 does not support the flow control.
R/W RTS Port Data
Controls the RTS pin in combination with the RTSIO bit
in this register and the MCE bit in SCFCR. Select the
RTS pin function in the PFC (pin function controller)
beforehand.
MCE RTSIO RTSDT: RTS pin state
00
×:
Input (initial state)
01
0:
Low level output
01
1:
High level output
1×
×:
Sequence output according to
modem control logic
×: Don't care
The RTS pin state is read from this bit instead of the set
value. This bit is reserved in SCPTR_2 of SCIF channel
2 since SCIF channel 2 does not support the flow
control.
Rev. 6.00 Jun. 12, 2007 Page 357 of 610
REJ09B0131-0600