SH7618 Datasheet, PDF (324/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
1. TFP = 00 or 01 (frame continuation):
Descriptor write-back is performed after DMA transfer.
2. TFP = 01 or 11 (frame end):
Descriptor write-back is performed after completion of frame transmission.
The E-DMAC continues reading descriptors and transmitting frames as long as the setting of the
TACT bit in the read descriptors is "active." When a descriptor with an "inactive" TACT bit is
read, the E-DMAC resets the transmit request bit (TR) in the transmit register and ends transmit
processing (EDTRR).
Transmission flowchart
This LSI + memory
E-DMAC
Transmit FIFO
EtherC
PHY
EtherC/E-DMAC
initialization
Descriptor and
transmit
buffer setting
Transmit directive
Descriptor read
Transmit data transfer
Descriptor write-back
Descriptor read
Transmit data transfer
Frame transmission
Descriptor write-back
Transmission
completed
Figure 12.4 Sample Transmission Flowchart
Rev. 6.00 Jun. 12, 2007 Page 292 of 610
REJ09B0131-0600