SH7618 Datasheet, PDF (452/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 15 Host Interface (HIF)
Table 15.6 Input/Output Control for HIF Pins
LSI
Status
Reset State by RES Pin
HIFMD
input
level
High
(Boot setting)
HIFEBL
input
level
Low
HIFRDY
output
control
Output
buffer:
On
(Low
output)
HIFINT
output
control
Output
buffer:
Off
High
Output
buffer:
On
(Low
output)
Output
buffer:
Off
Low
(Non-boot
setting)
The HIFEBL pin
is a general input
port and the HIF
is not controlled
by the signal
input on this pin.
General input port
General input port
HIFDREQ Output
output buffer:
control Off
Output
buffer:
Off
General input port
HIFD 15
to HIFD0
I/O
control
I/O
buffer:
Off
I/O
buffer:
Off
General input port
HIFCS
input
control
HIFRS
input
control
Input
buffer:
Off
Input
buffer:
Off
Input
buffer:
Off
Input
buffer:
Off
General input port
General input port
Reset Canceled by RES Pin
High
(After the reset
canceled by boot
setting)
Low
(After the reset canceled
by non-boot setting)
Low
Output
buffer:
Off
High
General input port at the
initial state *¹
Output
buffer: On
(Sequence
output)
General input port at the
initial state*²
Output
buffer:
Off
Output
buffer: On
(Sequence
output)
General input port at the
initial state*²
Output
buffer:
Off
Output
buffer: On
(Sequence
output)
General input port at the
initial state*²
I/O buffer:
Off
I/O buffer General input port at the
controlled initial state*²
according to
states of
HIFCS,
HIFWR,
and HIFRD
Input buffer: Input buffer: General input port at the
Off
On
initial state*²
Input buffer: Input buffer: General input port at the
Off
On
initial state*²
Rev. 6.00 Jun. 12, 2007 Page 420 of 610
REJ09B0131-0600