SH7618 Datasheet, PDF (127/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 6 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Description
3
IPR3
0
R/W Set priority levels for the corresponding interrupt
2
IPR2
0
R/W ^source.
1
IPR1
0
R/W ^{0000: Priority level 0 (lowest)}
0
IPR0
0
R/W ^{0001: Priority level 1}
0010: Priority level 2
0011: Priority level 3
0100: Priority level 4
0101: Priority level 5
0110: Priority level 6
0111: Priority level 7
1000: Priority level 8
1001: Priority level 9
1010: Priority level 10
1011: Priority level 11
1100: Priority level 12
1101: Priority level 13
1110: Priority level 14
1111: Priority level 15 (highest)
Note: Name in the tables above is represented by a general name. Name in the list of register is,
on the other hand, represented by a module name.
6.4 Interrupt Sources
6.4.1 External Interrupts
There are five types of interrupt sources: User break, NMI, H-UDI, IRQ, and on-chip peripheral
modules. Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 15 the
highest). Giving an interrupt a priority level of 0 masks it.
NMI Interrupt: The NMI interrupt is given a priority level of 16 and is always accepted. An NMI
interrupt is detected at the edge of the pins. Use the NMI edge select bit (NMIE) in interrupt
control register 0 (ICR0) to select either the rising or falling edge. In the NMI interrupt exception
handler, the interrupt mask level bits (I3 to I0) in the status register (SR) are set to level 15.
Rev. 6.00 Jun. 12, 2007 Page 95 of 610
REJ09B0131-0600