SH7618 Datasheet, PDF (325/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
12.3.3 Reception
When the receive function is enabled and the CPU sets the receive request bit (RR) in the E-
DMAC receive request register (EDRRR), the E-DMAC reads the descriptor following the
previously used one from the receive descriptor list (in the initial state, the descriptor indicated by
the transmission descriptor start address register (TDLAR)), and then enters the receive-standby
state. If the setting of the RACT bit is "active" and an own-address frame is received, the E-
DMAC transfers the frame to the receive buffer specified by RD2. If the data length of the
received frame is greater than the buffer length given by RD1, the E-DMAC performs write-back
to the descriptor when the buffer is full (RFP = 10 or 00), then reads the next descriptor. The E-
DMAC then continues to transfer data to the receive buffer specified by the new RD2. When
frame reception is completed, or if frame reception is suspended because of a certain kind of error,
the E-DMAC performs write-back to the relevant descriptor (RFP = 11 or 01), and then ends the
receive processing. The E-DMAC then reads the next descriptor and enters the receive-standby
state again.
To receive frames continuously, the receive enable control bit (RNC) must be set to 1 in the
receive control register (RCR). After initialization, this bit is cleared to 0.
Rev. 6.00 Jun. 12, 2007 Page 293 of 610
REJ09B0131-0600