SH7618 Datasheet, PDF (434/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 15 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
3
RD
0
R/W* Read
When this bit is set to 1, the HIFRAM data corresponding
to HIFADR is fetched to HIFDATA.
If this bit and the LOCK bit are set to 1 simultaneously,
HIFRAM consecutive read mode is entered, and high-
speed data transfer becomes possible. This mode is
maintained until this bit is next cleared to 0, or until the
LOCK bit is cleared to 0.
If the LOCK bit is not simultaneously set to 1 with this bit,
reading of HIFRAM is performed only once. Thereafter,
the value of this bit is automatically cleared to 0.
2, 1 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
AI/AD
0
R/W* Address Auto-Increment/Decrement
This bit is valid only when the LOCK bit is 1. The value of
HIFADR is automatically incremented by 4 or
decremented by 4 according to the setting of this bit each
time reading or writing of HIFRAM is performed.
0: Auto-increment mode (+4)
1: Auto-decrement mode (−4)
Note: * This bit can be only written to by an external device when the HIFRS pin is low. It
cannot be written to by the on-chip CPU. Changing the HIFRAM banks accessible from
an external device by setting the BMD and BSEL bits in HIFSCR does not affect the
setting of this bit.
Rev. 6.00 Jun. 12, 2007 Page 402 of 610
REJ09B0131-0600