SH7618 Datasheet, PDF (499/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 17 I/O Ports
17.5.1 Register Description
Port E is a 25-bit I/O port that has the following registers. For details on the addresses of these
registers and the states of these registers in each processing state, see section 20, List of Registers.
• Port E data register H (PEDRH)
• Port E data register L (PEDRL)
17.5.2 Port E Data Registers H and L (PEDRH and PEDRL)
PEDRH and PEDRL are 16-bit readable/writable registers that store data for port E. Bits PE24DR
to PE0DR correspond to pins PE24 to PE00. (Description of multiplexed functions is omitted.)
When the pin function is general output port, if the value is written to PEDRH or PEDRL, the
value is output from the pin; if PEDRH or PEDRL is read, the value written to the register is
directly read regardless of the pin state.
When the pin function is general input port, not the value of register but pin state is directly read if
PEDRH or PEDRL is read. Data can be written to PEDRH or PEDRL but no effect on the pin
state. Table 17.5 shows the reading/writing function of the port E data registers H and L.
• PEDRH
Initial
Bit Bit Name Value R/W Description
15 to 9 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
PE24DR 0
R/W See table 17.5.
7
PE23DR 0
R/W
6
PE22DR 0
R/W
5
PE21DR 0
R/W
4
PE20DR 0
R/W
3
PE19DR 0
R/W
2
PE18DR 0
R/W
1
PE17DR 0
R/W
0
PE16DR 0
R/W
Rev. 6.00 Jun. 12, 2007 Page 467 of 610
REJ09B0131-0600