SH7618 Datasheet, PDF (114/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 6 Interrupt Controller (INTC)
NMI
IRQ_... 0
IRQ7
UBC
H-UDI
WDT
E-DMAC
CMT0
CMT1
SCIF0
SCIF1
SCIF2
HIF
...
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
determination
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR0
IRQCR
IRQSR
IPR
IPRA to IPRE
DTER
DTC
Module bus
Bus
interface
[Legend]
UBC:
H-UDI:
WDT:
E-DMAC:
CMT:
SCIF:
INTC
User break controller
User debugging interface
Watchdog timer
DMAC for Ethernet controller
Compare match timer
Serial communications interface with FIFO
HIF:
Host interface
ICR0:
Interrupt control register 0
IRQCR:
IRQ control register
IRQSR:
IRQ status register
IPRA to IPRE: Interrupt priority registers A to E
SR:
Status register
Figure 6.1 INTC Block Diagram
Rev. 6.00 Jun. 12, 2007 Page 82 of 610
REJ09B0131-0600