SH7618 Datasheet, PDF (282/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 11 Ethernet Controller (EtherC)
1. When the receive enable (RE) bit is set, the receiver enters the receive idle state.
2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver
starts receive processing. Discards a frame with an invalid pattern.
3. In normal mode, if the destination address matches the receiver’s own address, or if broadcast
or multicast transmission or promiscuous mode is specified, the receiver starts data reception.
4. Following data reception from the MII, the receiver carries out a CRC check. The result is
indicated as a status bit in the descriptor after the frame data has been written to memory.
Reports an error status in the case of an abnormality.
5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode
register, the receiver prepares to receive the next frame.
11.4.3 MII Frame Timing
Each MII Frame timing is shown in figure 11.4.
TX-CLK
TX-EN
TXD3 to TXD0
TX-ER
Preamble
SFD
Data
CRC
CRS
COL
Figure 11.4 (1) MII Frame Transmit Timing (Normal Transmission)
TX-CLK
TX-EN
MII_TXD3 to
MII_TXD0
TX-ER
CRS
COL
Preamble
JAM
Figure 11.4 (2) MII Frame Transmit Timing (Collision)
Rev. 6.00 Jun. 12, 2007 Page 250 of 610
REJ09B0131-0600