SH7618 Datasheet, PDF (591/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

21.4.5 Synchronous DRAM Timing
Section 21 Electrical Characteristics
CKIO
A25 to A0
A11^*
Tr
Tc1
Tcw
t_AD1
t_AD1
Row address
Column address
t_AD1
t_AD1
t_AD1
Read A command
Td1
Tde
t_AD1
CSn
RD/WR
RAS
CAS
DQMxx
t_CSD1
t_RWD
t_RASD
t_RASD
t_CASD
t_CASD
t_DQMD
D15 to D0
BS
tBSD
t_BSD
t_CSD1
t_RWD
t_DQMD
t_RDS2
t_RDH2
CKE
(High)
Note: * An address pin connected to pin A10 of SDRAM
Figure 21.16 Synchronous DRAM Single Read Bus Cycle (Auto-Precharge,
CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)
Rev. 6.00 Jun. 12, 2007 Page 559 of 610
REJ09B0131-0600