SH7618 Datasheet, PDF (388/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
14.3.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register which indicates the number of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the number of
transmit data in SCFTDR with the upper eight bits, and the number of receive data in SCFRDR
with the lower eight bits. SCFDR can always be read from by the CPU. SCFDR is initialized to
H'0000 by a power on reset.
Bit
Bit Name
15 to 13 
12
T4
11
T3
10
T2
9
T1
8
T0
7 to 5 
4
R4
3
R3
2
R2
1
R1
0
R0
Initial
value
All 0
0
0
0
0
0
All 0
0
0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R Indicate the number of non-transmitted data stored in
R
SCFTDR. H'00 means no transmit data, and H'10
means that SCFTDR is full of transmit data.
R
R
R
R Reserved
These bits are always read as 0. The write value should
always be 0.
R Indicate the number of receive data stored in SCFRDR.
R
H'00 means no receive data, and H'10 means that
SCFRDR full of receive data.
R
R
R
Rev. 6.00 Jun. 12, 2007 Page 356 of 610
REJ09B0131-0600