SH7618 Datasheet, PDF (61/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 2 CPU
Addressing
Mode
Register
indirect with
pre-decrement
Register
indirect with
displacement
Instruction
Format Effective Address Calculation Method
@–Rn
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn - 1/2/4
-
Rn - 1/2/4
1/2/4
@(disp:4,
Rn)
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
Rn
disp
(zero-extended)
+
Rn
+ disp × 1/2/4
×
Calculation
Formula
Byte: Rn – 1 →
Rn
Word: Rn – 2 →
Rn
Longword: Rn – 4
→ Rn
(Instruction
executed with Rn
after calculation)
Byte: Rn + disp
Word: Rn + disp ×
2
Longword: Rn +
disp × 4
1/2/4
Index
@(R0, Rn) Effective address is sum of register Rn and R0 Rn + R0
register indirect
contents.
Rn
+
Rn + R0
R0
GBR indirect
with
displacement
@(disp:8,
GBR)
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
GBR
disp
(zero-extended)
+
GBR
+ disp × 1/2/4
Byte: GBR + disp
Word: GBR + disp
×2
Longword: GBR +
disp × 4
×
1/2/4
Rev. 6.00 Jun. 12, 2007 Page 29 of 610
REJ09B0131-0600