SH7618 Datasheet, PDF (435/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 15 Host Interface (HIF)
15.4.5 HIF Internal Interrupt Control Register (HIFIICR)
HIFIICR is a 32-bit register used to issue interrupts from an external device connected to the HIF
to the on-chip CPU. Access to HIFIICR by an external device should be performed with HIFIICR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Initial
Bit
Bit Name Value
31 to 8 —
All 0
7
IIC6
0
6
IIC5
0
5
IIC4
0
4
IIC3
0
3
IIC2
0
2
IIC1
0
1
IIC0
0
0
IIR
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Internal Interrupt Source
These bits specify the source for interrupts generated by
the IIR bit. These bits can be written to from both an
external device and the on-chip CPU. By using these
bits, fast execution of interrupt exception handling is
possible. These bits are completely under software
control, and their values have no effect on the operation
of this LSI.
Internal Interrupt Request
While this bit is 1, an interrupt request (HIFI) is issued to
the on-chip CPU.
15.4.6 HIF External Interrupt Control Register (HIFEICR)
HIFEICR is a 32-bit register used to issue interrupts to an external device connected to the HIF
from this LSI. Access to HIFEICR by an external device should be performed with HIFEICR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Initial
Bit
Bit Name Value
31 to 8 —
All 0
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 6.00 Jun. 12, 2007 Page 403 of 610
REJ09B0131-0600