SH7618 Datasheet, PDF (37/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 1 Overview
• The external device can access the desired register after the register index has been specified.
(However, when the buffer RAM is accessed successively, the address is updated
automatically.)
• Selection of endian mode
• Interrupt requested to the external device
• Internal interrupt requested to the CPU of this LSI
• Booting from the buffer RAM is enabled if the external device has stored the instruction code
in the buffer RAM
Compare match timer (CMT):
• 16-bit counter
• Generates compare match interrupts
• Two channels
Serial communication interface with FIFO (SCIF):
• Synchronous and asynchronous modes
• 16 bytes each for transmit/receive FIFO
• High-speed UART
• The UART supports FIFO stop and FIFO trigger
• Flow control enabled (channel 0 and channel 1 only)
• Three channels
I/O ports:
• 78 general input/output pins
• Input or output can be set per bit within the input/output common port
Package:
• BP1313-176 (0.8 pitch)
Power supply voltage:
• I/O: 3.0 to 3.6 V
Internal: 1.5±0.1 V (Two power sources are externally provided.)
Note: * Magic Packet^TM is the registered trademark of Advance Micro Devices, Inc.
Rev. 6.00 Jun. 12, 2007 Page 5 of 610
REJ09B0131-0600