SH7618 Datasheet, PDF (267/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 11 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value R/W
Description
0
PRM
0
R/W
Promiscuous Mode
Setting this bit enables all Ethernet frames to be
received. All Ethernet frames means all receivable
frames, irrespective of differences or enabled/disabled
status (destination address, broadcast address,
multicast bit, etc.).
0: EtherC performs normal operation
1: EtherC performs promiscuous mode operation
11.3.2 EtherC Status Register (ECSR)
ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can
be notified to the CPU by interrupts. When 1 is written to the PSRTO, LCHNG, MPD, and ICD,
the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate
interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR.
The interrupts generated due to this status register are indicated in the ECI bit in EESR.
Bit
Bit Name
31 to 5 
4
PSRTO
3

Initial
Value
All 0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W PAUSE Frame Retransfer Retry Over
Indicates that during the retransfer of PAUSE frames
when the flow control is enabled, the number of
retries has exceeded the upper limit set in the
automatic PAUSE frame retransfer count set register
(TPAUSER).
0: Number of PAUSE frame retransfers has not
exceeded the upper limit
1: Number of PAUSE frame retransfers has
exceeded the upper limit
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 6.00 Jun. 12, 2007 Page 235 of 610
REJ09B0131-0600