SH7618 Datasheet, PDF (637/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Index
A
Access wait control................................. 150
Accessing MII registers .......................... 252
Address array............................................ 58
Address error exception handling ............. 71
Address error sources ............................... 71
Address multiplexing.............................. 154
Addressing modes..................................... 28
Arithmetic operation instructions ............. 41
Asynchronous Mode............................... 362
Auto-refreshing....................................... 174
B
Bank active ............................................. 167
Basic timing............................................ 146
Basic timing for I/O card interface ......... 187
Basic timing for memory card interface . 185
Bit rate .................................................... 346
Boundary scan ........................................ 507
Branch instructions ................................... 44
Burst read................................................ 161
Burst write .............................................. 165
Bus state controller (BSC) ...................... 105
Byte-selection SRAM interface .............. 179
C
Cache ........................................................ 49
Cache structure ......................................... 49
Cases when exceptions are accepted......... 76
Changing clock operating mode ............. 203
Changing division ratio........................... 203
Changing frequency................................ 202
Changing multiplication ratio ................. 202
Clock operating modes ........................... 196
Clock Pulse Generator (CPG)................. 193
Coherency of cache and external
memory ..................................................... 57
Compare match timer (CMT) ................. 315
Connection to PHY-LSI.......................... 257
Control registers........................................ 21
CPU........................................................... 19
D
Data array.................................................. 59
Data register............................................ 457
Data transfer instructions .......................... 39
Divided areas and cache............................ 51
E
Endian/access size and data alignment ... 141
EtherC receiver ....................................... 249
EtherC transmitter................................... 247
Ethernet controller (EtherC).................... 227
Ethernet controller direct memory
access controller (E-DMAC) .................. 259
Exception handling ................................... 65
Exception handling operations.................. 66
Exception handling vector table................ 67
Extension of chip select (CSn)
assertion period ....................................... 152
F
Features of instructions ............................. 25
Flow control............................................ 256
G
General illegal instructions ....................... 75
General registers (Rn) ............................... 21
Rev. 6.00 Jun. 12, 2007 Page 605 of 610
REJ09B0131-0600