SH7618 Datasheet, PDF (140/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 7 Bus State Controller (BSC)
7.2 Input/Output Pins
Table 7.1 lists the pin configuration of the BSC.
Table 7.1 Pin Configuration
Abbreviation I/O
Function
A25 to A0
Output Address Bus*
D15 to D0
I/O
Data Bus
BS
Output Bus Cycle Start
Asserted when a normal space, burst ROM (clock synchronous
/asynchronous), or PCMCIA is accessed. Asserted at the same timing
as CAS assertion in SDRAM access.
CS0, CS3, CS4 Output Chip Select
CS5B/CE1A Output Chip Select
Chip enable for PCMCIA allocated to area 5 when PCMCIA is in use
CE2A
CS6B/CE1B
Output Chip enable for PCMCIA allocated to area 5 when PCMCIA is in use
Output Chip Select
Chip enable for PCMCIA allocated to area 6 when PCMCIA is in use
CE2B
RD/WR
RD
Output Chip enable for PCMCIA allocated to area 6 when PCMCIA is in use
Output Read/Write
Connects to WE pins when SDRAM or byte-selection SRAM is used.
Output Read Pulse Signal (read data output enable signal)
Strobe signal to indicate a memory read cycle when PCMCIA is in use.
WE1(BE1)/WE Output Indicates that D15 to D8 are being written to.
Connected to the byte select signal when byte-selection SRAM is in
use.
WE0(BE0)
Strove signal to indicate a memory write cycle when PCMCIA is in use.
Output Indicates that D7 to D0 are being written to.
Connected to the byte select signal when a byte-selection SRAM is in
use.
RAS
CAS
Output Connected to RAS pin when SDRAM is in use.
Output Connected to CAS pin when SDRAM is in use.
CKE
Output Connected to CKE pin when SDRAM is in use.
Rev. 6.00 Jun. 12, 2007 Page 108 of 610
REJ09B0131-0600