SH7618 Datasheet, PDF (298/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name value R/W Description
25
RABT
0
R/W Receive Abort Detection
Indicates that the EtherC aborts receiving a frame
because of failures during receiving the frame.
0: Frame reception has not been aborted or no
receive directive
1: Frame receive has been aborted
24
RFCOF
0
R/W Receive Frame Counter Overflow
Indicates that the receive FIFO frame counter has
overflowed.
0: Receive frame counter has not overflowed
1: Receive frame counter overflows
23
ADE
0
R/W Address Error
Indicates that the memory address that the E-DMAC
tried to transfer is found illegal.
0: Illegal memory address not detected (normal
operation)
1: Illegal memory address detected
Note: When an address error is detected, the
E-DMAC halts transmitting/receiving. To
resume the operation, set the E-DMAC again
after software reset by means of the SWR bit in
EDMR.
22
ECI
0
R
EtherC Status Register Interrupt Source
This bit is a read-only bit. When the source of an
ECSR interrupt in the EtherC is cleared, this bit is
also cleared.
0: EtherC status interrupt source has not been
detected
1: EtherC status interrupt source has been detected
Rev. 6.00 Jun. 12, 2007 Page 266 of 610
REJ09B0131-0600