SH7618 Datasheet, PDF (431/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 15 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
11
DMD
0
R/W DREQ Mode
10
DPOL
0
R/W DREQ Polarity
Controls the assert mode for the HIFDREQ pin. For
details on the negate timing, see section 15.8, External
DMAC Interface.
00: For a DMAC transfer request to an external device,
low level is generated at the HIFDREQ pin. The
default for the HIFDREQ pin is high-level output.
01: For a DMAC transfer request to an external device,
high level is generated at the HIFDREQ pin. The
default for the HIFDREQ pin is low-level output.
10: For a DMAC transfer request to an external device,
falling edge is generated at the HIFDREQ pin. The
default for the HIFDREQ pin is high-level output.
11: For a DMAC transfer request to an external device,
rising edge is generated at the HIFDREQ pin. The
default for the HIFDREQ pin is low-level output.
9
BMD
0
R/W HIFRAM Bank Mode
8
BSEL
0
R/W HIFRAM Bank Select
Controls the HIFRAM access mode.
00: Both an external device and the on-chip CPU can
access bank 0. When access by both of these
conflict, even though the access addresses differ,
access by the external device is processed before
access by the on-chip CPU. Bank 1 cannot be
accessed.
01: Both an external device and the on-chip CPU can
access bank 1. When access by both of these
conflict, even though the access addresses differ,
access by the external device is processed before
access by the on-chip CPU. Bank 0 cannot be
accessed.
10: An external device can access only bank 0 while
the on-chip CPU can access only bank 1.
11: An external device can access only bank 1 while
the on-chip CPU can access only bank 0.
Rev. 6.00 Jun. 12, 2007 Page 399 of 610
REJ09B0131-0600