SH7618 Datasheet, PDF (354/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 13 Compare Match Timer (CMT)
13.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has
priority over the count-up. In this case, the count-up is not performed. Figure 13.6 shows the
timing to write to CMCNT in words.
Peripheral operating
clock (Pφ)
CMCSR write cycle
T1
T2
Address
CMCNT
Internal write
CMCNT count-up
enable
CMCNT
N
M
Figure 13.6 Conflict between Word-Write and Count-Up Processes of CMCNT
Rev. 6.00 Jun. 12, 2007 Page 322 of 610
REJ09B0131-0600