SH7618 Datasheet, PDF (612/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 21 Electrical Characteristics
21.4.7 SCIF Timing
Table 21.10 SCIF Timing
Conditions: V_CCQ = 3.0 V to 3.6 V, V_CC = 1.4 V to 1.6 V,
T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
Item
Symbol Min. Max.
Unit
Input clock cycle Clocked
t_Scyc
12 
t_pcyc
synchronous
Asynchronous
Input clock rising time
t
SCKR
Input clock falling time
t
SCKF
Input clock pulse width
t_SCKW
Transmit data delay time
t
TXD
Receive data setup time
t_RXS
(clocked synchronous)
4
t
pcyc
 0.8
t
pcyc
 0.8
t
pcyc
0.4 0.6
t_Scyc
 3 × t_pcyc* + 50 ns
3
t_pcyc
Receive data hold time
(clocked synchronous)
t_RXH
3
t_pcyc
RTS delay time
CTS setup time
(clocked synchronous)
t
RTSD
 100
ns
t
CTSS
100 
ns
CTS hold time
(clocked synchronous)
t_CTSH
100 
ns
Note: * t_pcyc indicates the period of the peripheral module clock (Pφ).
Reference Figures
Figures 21.37 and
21.38
Figure 21.37
Figure 21.38
SCK
t_SCKW
t_SCKR
t_Scyc
t_SCKF
Figure 21.37 SCK Input Clock Timing
Rev. 6.00 Jun. 12, 2007 Page 580 of 610
REJ09B0131-0600