SH7618 Datasheet, PDF (445/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 15 Host Interface (HIF)
HIFCS
HIFRS
HIFRD
HIFWR
HIFD15 to HIFD00
0016 AHAL 000A 0088 0018 D0D1 D2D3 D4D5 D6D7 D8D9 DADB DCDD
HIFADR setting HIFMCR setting HIFDATA
[15:8] = AH Consecutive read selection
[7:0] = AL
Auto-increment
Consecutive data reading
Figure 15.7 Consecutive Data Reading from HIFRAM
15.8 External DMAC Interface
Figures 15.8 to 15.11 show the HIFDREQ output timing. The start of the HIFDREQ assert
synchronizes with the DTRG bit in HIFDTR being set to 1. The HIFDREQ negate timing and
assert level are determined by the DMD and DPOL bits in HIFSCR, respectively.
When the external DMAC is specified to detect low level of the HIFDREQ signal, set DMD = 0
and DPOL = 0. After writing 1 to the DTRG bit, the HIFDREQ signal remains low until low level
is detected for both the HIFCS and HIFRS signals.
In this case, when the HIFDREQ signal is used, make sure that the setup time (HIFCS assertion to
HIFRS settling) and the hold time (HIFRS hold to HIFCS negate) are satisfied. If t_HIFAS and t_HIFAH
stipulated in section 21.4.9, HIF Timing, are not satisfied, the HIFDREQ signal may be negated
unintentionally.
DTRG bit
DPOL bit
HIFDREQ
HIFCS
HIFRS
Asserted in synchronization with the
DTRG bit being set by the on-chip CPU.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
Negated when HIFCS = HIFRS = low level.
Latency is tPCYC (peripheral clock cycle) × 3 cyc or less.
Figure 15.8 HIFDREQ Timing (When DMD = 0 and DPOL = 0)
Rev. 6.00 Jun. 12, 2007 Page 413 of 610
REJ09B0131-0600