SH7618 Datasheet, PDF (193/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 7 Bus State Controller (BSC)
Burst Read: A burst read occurs in the following cases with this LSI.
1. Access size in reading is larger than data bus width.
2. 16-byte transfer in cache miss.
3. 16-byte transfer by E-DMAC (access to non-cacheable area)
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively eight times to read 16-byte consecutive data from the
SDRAM that is connected to a 16-bit data bus.
Table 7.16 shows the relationship between the access size and the number of bursts.
Table 7.16 Relationship between Access Size and Number of Bursts
Bus Width
16 bits
Access Size
8 bits
16 bits
32 bits
16 bytes
Number of Bursts
1
1
2
8
Figures 7.12 and 7.13 show timing charts in burst read. In burst read, the ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is latched at the rising edge of the external
clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an
auto-precharge induced by the READ command in the SDRAM. In the Tap cycle, a new
command will not be issued to the same bank. However, other banks can be accessed. The number
of Tap cycles is specified by bits WTRP1 and WTRP0 in CS3WCR.
In this LSI, wait cycles can be inserted by specifying bits in CSnWCR to connect the SDRAM
with variable frequencies. Figure 7.15 shows an example in which wait cycles are inserted. The
number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where
the READA command is output can be specified using bits WTRCD1 and WTRCD0 in CS3WCR.
When bits WTRCD1 and WTRCD0 is set to one cycle or more, a Trw cycle where the NOP
command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the
Tc1 cycle where the READA command is output to the Td1 cycle where the read data is latched
can be specified by bits A3CL1 and A3CL0 bits in CS3WCR in CS3WCR. This number of cycles
corresponds to the synchronous DRAM CAS latency. The CAS latency for the synchronous
DRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be
specified as one to four cycles. This CAS latency can be achieved by connecting a latch circuit
between this LSI and the synchronous DRAM.
Rev. 6.00 Jun. 12, 2007 Page 161 of 610
REJ09B0131-0600