SH7618 Datasheet, PDF (641/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

TDFAR ....................... 281, 514, 527, 537
TDLAR....................... 264, 514, 525, 537
TFTR .......................... 275, 514, 526, 537
TLFRCR ..................... 244, 515, 530, 538
TPAUSER .................. 246, 515, 531, 538
TRIMD ....................... 282, 514, 527, 537
TROCR....................... 241, 514, 529, 537
TRSCER ..................... 273, 514, 526, 537
TSFRCR ..................... 243, 515, 530, 537
WTCNT ...................... 209, 511, 519, 534
WTCSR ...................... 209, 511, 519, 534
Register data format.................................. 24
Relationship between refresh requests and
bus cycles................................................ 177
Reset ......................................................... 69
RISC-type ................................................. 25
S
SCIF Initialization (Asynchronous Mode)
................................................................ 366
SCIF initialization (synchronous mode) . 376
SDRAM direct connection ..................... 153
SDRAM interface ................................... 153
Searching cache ........................................ 54
Self-refreshing ........................................ 176
Serial communication interface with FIFO
(SCIF) ..................................................... 325
Shift instructions....................................... 44
Single read .............................................. 164
Single Write............................................ 167
Sleep mode ............................................. 222
Software standby mode........................... 223
Stack states after exception handling
ends........................................................... 77
State transition .......................................... 47
Synchronous mode ................................. 375
System control instructions....................... 45
System registers ........................................ 22
T
TAP controller ........................................ 504
Transmit descriptor 0 (TD0) ................... 284
Transmit descriptor 1 (TD1) ................... 286
Transmit descriptor 2 (TD2) ................... 286
Transmitting and receiving serial data
simultaneously (synchronous mode)....... 382
Transmitting serial data
(asynchronous mode) .............................. 368
Transmitting serial data
(synchronous mode)................................ 378
Trap instructions ....................................... 74
Types of exception handling and
priority ...................................................... 65
Types of exceptions triggered by
instructions................................................ 74
Types of power-down modes.................. 215
U
U memory ................................................. 63
User break controller (UBC)................... 471
User break interrupt .................................. 97
User debugging interface (H-UDI) ......... 493
W
Wait between access cycles .................... 190
Watchdog timer (WDT) .......................... 207
Write access .............................................. 56
Write-back buffer...................................... 57
Rev. 6.00 Jun. 12, 2007 Page 609 of 610
REJ09B0131-0600