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SH7618 Datasheet, PDF (581/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
Section 21 Electrical Characteristics
21.4.2 Control Signal Timing
Table 21.8 Control Signal Timing
Conditions: VCCQ = 3.0 V to 3.6 V, VCC = 1.4 V to 1.6 V,
Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol Min.
Max.
Reference
Unit Figures
RES pulse width
RES setup time*1
t
RESW
tRESS
20*2

25

t *3
bcyc
Figures 21.7 and
ns 21.8
RES hold time
tRESH
15

ns
NMI setup time*1
t
12
NMIS

ns Figure 21.8
NMI hold time
t
10
NMIH

ns
IRQ7 to IRQ0 setup time*1
t
12
IRQS

ns
IRQ7 to IRQ0 hold time
t
10
IRQH

ns
Bus tri-state delay time 1
tBOFF1

20
ns Figure 21.9
Bus tri-state delay time 2
t
BOFF2

20
ns
Bus buffer on time 1
tBON1

20
ns
Bus buffer on time 2
tBON2

20
ns
Notes: 1. The RES, NMI, and IRQ7 to IRQ0 signals are asynchronous signals. When the setup
time is satisfied, a signal change is detected at the rising edge of the clock signal. When
the setup time is not satisfied, a signal change may be delayed to the next rising edge.
2. In standby mode, t = t (10 ms). When changing the clock multiplication, t = t
RESW
OSC2
RESW
PLL1
(100 µs).
3. tbcyc indicates the period of the external bus clock (Bφ).
CKIO
RES
tRESS
tRESW
tRESS
Figure 21.7 Reset Input Timing
Rev. 6.00 Jun. 12, 2007 Page 549 of 610
REJ09B0131-0600