SH7618 Datasheet, PDF (231/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Initial
Bit
Bit Name Value R/W
15 to 13 
All 0
R
12
CKOEN 1
R/W
11

0
R
10
STC2
0
R/W
9
STC1
0
R/W
8
STC0
0
R/W
7 to 3 
All 0
R
Section 8 Clock Pulse Generator (CPG)
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Output Enable
Specifies whether a clock continues to be output from
the CKIO pin or the output level of the CKIO signal is
fixed when leaving software standby mode. The CKIO
output is fixed low when this bit is set to 0. Therefore,
the malfunction of external circuits because of an
unstable CKIO clock when leaving software standby
mode can be prevented.
0: Output level of the CKIO signal is fixed low in
software standby mode.
1: Clock input to the EXTAL pin is output to the CKIO
pin during software standby mode in clock mode 1
or 5. However, the output level of the CKIO pin is
fixed low for two cycles of Pφ when changing from
the normal mode to the standby mode. This
prevents hazard which occurs when the source of
the CKIO signal is changed from the PLL2 output
to the EXTAL signal.
Reserved
This bit is always read as 0. The write value should
always be 0.
PLL Circuit 1 Frequency Multiplication Ratio
000: ×1
001: ×2
Other values: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 6.00 Jun. 12, 2007 Page 199 of 610
REJ09B0131-0600