SH7618 Datasheet, PDF (264/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 11 Ethernet Controller (EtherC)
11.3.1 EtherC Mode Register (ECMR)
ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet
controller. The settings in this register are normally made in the initialization process following a
reset.
The operating mode setting must not be changed while the transmitting and receiving functions
are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Initial
Bit
Bit Name Value R/W
31 to 20 
All 0
R
19
ZPF
0
R/W
18
PFR
0
R/W
17
RXF
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
0 time parameter PAUSE Frame Use Enable
0: Disables PAUSE frame control in which the TIME
parameter is 0.
The next frame is transmitted after the time
indicated by the Timer value has elapsed. When the
EtherC receives a PAUSE frame with the time
indicated by the Timer value set to 0, the PAUSE
frame is discarded.
1: Enables PAUSE frame control in which the TIME
parameter is 0.
A PAUSE frame with the Timer value set to 0 is
transmitted when the number of data in the receive
FIFO is less than the FCFTR value before the time
indicated by the Timer value has not elapsed. When
the EtherC receives a PAUSE frame with the time
indicated by the Timer value set to 0, the transmit
wait state is canceled.
PAUSE Frame Receive Mode
0: PAUSE frame is not transferred to the E-DMAC
1: PAUSE frame is transferred to the E-DMAC
Receive Flow Control Operating Mode
0: PAUSE frame detection function is disabled
1: Receive flow control function is enabled
Rev. 6.00 Jun. 12, 2007 Page 232 of 610
REJ09B0131-0600