SH7618 Datasheet, PDF (535/646 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

Section 19 User Debugging Interface (H-UDI)
Bit Pin Name
I/O
Bit Pin Name
I/O
17 PB05/ICIORD
16 PB06/ICIOWR
15 PB01/IOIS16
Control 7
Control 6
Control 5
PA19/A19
PA20/A20
PA21/A21
Control
Control
Control
14 PB09/CE2A
13 PB10/CS5B,CE1A
Control 4
Control 3
PA22/A22
PA23/A23
Control
Control
12 PB07/CE2B
11 PB08/CS6B,CE1B
Control 2
Control 1
PA24/A24
PA25/A25
Control
Control
10 PA16/A16
Control 0
PD07/IRQ7/SCK2/-
Control
9
PA17/A17
Control
To TDO
8
PA18/A18
Control
Note: * Control means a low active signal.
The corresponding pin is driven with an OUT value when the Control is driven low.
19.3.4 ID Register (SDID)
SDID is a 32-bit read-only register in which SDIDH and SDIDL are connected. Each register is a
16-bit that can be read by the CPU.
To read this register by the H-UDI side, the contents can be read via the TDO pin when the
IDCODE command is set and the TAP state is Shift-DR. Writing is disabled.
Bit
31 to 0
Bit Name
DID31 to
DID0
Initial
Value
R/W
Refer to R
description
Description
Device ID 31 to Device ID 0
ID register that is stipulated by JTAG. H'002B200F
(initial value) for this LSI. Upper four bits may be
changed according to the LSI version.
SDIDH corresponds to bits 31 to 16.
SDIDL corresponds to bits 15 to 0.
Rev. 6.00 Jun. 12, 2007 Page 503 of 610
REJ09B0131-0600